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    <url>http://masc.cse.ucsc.edu/images/masclogo2.png</url>
    <title>MASC Logo</title>
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      <item>
	
	<title>New Paper: Understanding bug fix patterns in verilog</title>
        
          <link>docs/msr08.pdf</link>
        
	<description>Sangeetha Sudakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau, Fith International Workshop on Mining Software Repositories, May 2008.</description>
	
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        <pubDate>Wed, 16 Jul 2008 00:00:00 +0000</pubDate>
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	<title>New Paper: Implementation of a Power Efficient High Performance FPU for SCOORE</title>
        
          <link>docs/warp08.pdf</link>
        
	<description>Wael Ali Ashmawi, John Burr, Abhishek Sharma, Jose Renau, Workshop on Architectural Research Prototyping (<strong>WARP</strong>), held inconjunction with ISCA-35, June 2008.</description>
	
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        <pubDate>Wed, 18 Jun 2008 00:00:00 +0000</pubDate>
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	<title>New thermal page</title>
	
	<description>This page shows several of the thermal measurements performed by the MASC group
	</description>
	
	
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        <pubDate>Mon, 09 Jun 2008 00:00:00 +0000</pubDate>
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	<title>New PhD Students (Gabriel Southern and Ehsan Ardestani)</title>
	
	<description>Both would start in Fall 08
	</description>
	
	
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        <pubDate>Sun, 08 Jun 2008 00:00:00 +0000</pubDate>
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	<title>Therminic conference call for papers</title>
        
          <link>http://cmp.imag.fr/conferences/therminic2008/</link>
        
	<description>
	  Papers are due on 2008-03-30.
	  International Workshop on Thermal inverstigations of ICs and Systems
	</description>
	
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        <pubDate>Sun, 30 Mar 2008 00:00:00 +0000</pubDate>
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	<title>ICCAD conference call for papers</title>
        
          <link>http://www.iccad.com</link>
        
	<description>
	  Papers are due on 2008-04-14.
	  International Conference on Computer-Aided Design
	</description>
	
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        <pubDate>Mon, 14 Apr 2008 00:00:00 +0000</pubDate>
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	<title>NSF CRI Infrared Equipment ($275K)</title>
	
	<description>NSF Infrastructre award to purchase the IR measurement setup.
	</description>
	
	
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        <pubDate>Thu, 10 Apr 2008 00:00:00 +0000</pubDate>
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	<title>New PhD Student (Alamelu)</title>
	
	<description>Alamelu will start her PhD once she finishes the MS.
	</description>
	
	
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        <pubDate>Sat, 12 Jan 2008 00:00:00 +0000</pubDate>
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	<title>New Paper: Measuring Power and Temperature from Real Processors</title>
        
          <link>docs/ngs08.pdf</link>
        
	<description>Francisco-Javier Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, The Next Generation Software (NGS) Workshop (<b>NGS08</b>) held in conjunction with IPDPS, April 2008.</description>
	
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        <pubDate>Tue, 01 Apr 2008 00:00:00 +0000</pubDate>
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	<title>New Paper: WACI</title>
        
	<description>uDSim, a Microprocessor Design Time Simulation Infrastructure. Sangeetha Sudhakrishnan, Francisco-Javier Mesa-Martinez, Jose Renau, Wild and Crazy Ideas VI (<b>WACI</b>) held in conjunction with ASPLOS, March 2008.</description>
	
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        <pubDate>Sat, 01 Mar 2008 00:00:00 +0000</pubDate>
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	<title>New Paper: Processor Verification with hwBugHunt</title>
        
          <link>docs/isqed08.pdf</link>
        
	<description>Sangeetha Sudhakrishnan, Liying Su, and Jose Renau, IEEE International Symposium on Quality Electronic Design (<strong>ISQED</strong>), March 2008.</description>
	
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        <pubDate>Thu, 10 Jan 2008 00:00:00 +0000</pubDate>
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	<title>New Paper: Springer</title>
        
	<description>System and Processor Design Effort Estimation, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau, Springer Research Trends in VLSI and Systems on Chip.</description>
	
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        <pubDate>Fri, 01 Feb 2008 00:00:00 +0000</pubDate>
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	<title>nVIDIA Gift ($70K)</title>
	
	<description>Gift to support thermal projects at the MASC group.
	</description>
	
	
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        <pubDate>Thu, 10 Jan 2008 00:00:00 +0000</pubDate>
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	<title>NSF CSR Infrared Thermal Measurement ($300K)</title>
	
	<description>Three years NSF grant for the thermal measurement infrastructure setup.
	</description>
	
	
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        <pubDate>Wed, 10 Oct 2007 00:00:00 +0000</pubDate>
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	<title>PACT conference call for papers</title>
        
          <link>http://www.eecg.toronto.edu/pact/</link>
        
	<description>
	  Papers are due on 2008-03-20.
	  Parallel Architectures and Compilation Techniques (PACT)
	</description>
	
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        <pubDate>Thu, 20 Mar 2008 00:00:00 +0000</pubDate>
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	<title>New BLOG for the MASC group</title>
	
	
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        <pubDate>Thu, 23 Aug 2007 00:00:00 +0000</pubDate>
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	<title>New Paper: Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning</title>
        
          <link>docs/micro07.pdf</link>
        
	<description>Francisco J. Mesa-Martinez and Jose Renau, 40th International Symposium on Microarchitecture (<strong>MICRO</strong>), December 2007.</description>
	
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        <pubDate>Mon, 10 Sep 2007 00:00:00 +0000</pubDate>
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	<title>New Paper: Estimating Design Time for System Circuits</title>
        
          <link>docs/vlsisoc07.pdf</link>
        
	<description>Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau, 15th IFIP International Conference on Very Large Scale Integration (<strong>VLSI-SoC</strong>), October 2007.</description>
	
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        <pubDate>Fri, 10 Aug 2007 00:00:00 +0000</pubDate>
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	<title>Xilinx Equipment Donation</title>
	
	<description>We have licenses to the latest Xilinx software tools.
	</description>
	
	
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        <pubDate>Sun, 01 Jul 2007 00:00:00 +0000</pubDate>
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	<title>ISCA conference call for papers</title>
        
          <link>http://isca2008.cs.princeton.edu/index.html</link>
        
	<description>
	  Papers are due on 2007-11-09.
	  First-tier conference on computer architecture. This year, it is held on <strong>China</strong>.
	</description>
	
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        <pubDate>Fri, 09 Nov 2007 00:00:00 +0000</pubDate>
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	<title>Javi Graduated</title>
	
	<description>His thesis introduces a new methodology to improve processor efficiency by reducing the size of the codebase for a processor design in order to manage increases in complexity and extract further performance from already existing design. Based on this methodology he introduces a novel Tandem architecture which combines a complex out-of-order core, that has some of it underutilized functionality removed, with a verified simpler in-order core that guarantees forward progress whenever excised functionality from the complex processor is exercised.
	</description>
	
	
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        <pubDate>Fri, 01 Jun 2007 00:00:00 +0000</pubDate>
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	<title>NASA/UARC "Radiation Tolerant FPGA Processor" ($25K)</title>
	
	<description>Grant to continue supporting the development of the SCOORE project.
	</description>
	
	
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        <pubDate>Thu, 10 May 2007 00:00:00 +0000</pubDate>
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	<title>New Paper: Power Model Validation Through Thermal Measurements</title>
        
          <link>docs/isca07.pdf</link>
        
	<description>Francisco J. Mesa-Martinez, Joseph Nayfach-Battilan, and Jose Renau, International Symposium on Computer Architecture (<strong>ISCA</strong>), June 2007.</description>
	
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        <pubDate>Tue, 01 May 2007 00:00:00 +0000</pubDate>
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	<title>New Paper: Measuring Performance, Power, and Temperature from Real Processors</title>
        
          <link>docs/wecs07.pdf</link>
        
	<description>Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, and Jose Renau, 1st Workshop on Experimental Computer Science (FCRC), June 2007.</description>
	
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        <pubDate>Tue, 01 May 2007 00:00:00 +0000</pubDate>
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	<title>SUN OpenSPARC Center of Excellence at Santa Cruz</title>
	
	<description>Sun created the first ever OpenSPARC Center of Excellence at UCSC.
	</description>
	
	
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        <pubDate>Fri, 02 Feb 2007 00:00:00 +0000</pubDate>
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	<title>SUN Academic Excellence Grant ($110K)</title>
	
	<description>Sun donated $110K equipment to our group. Thanks Sun for this wonderful gift.
	</description>
	
	
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        <pubDate>Thu, 01 Feb 2007 00:00:00 +0000</pubDate>
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	<title>New Paper: SEED Scalable, Efficient Enforcement of Dependences</title>
        
          <link>docs/pact06.pdf</link>
        
	<description>Francisco J. Mesa-Martinez, Michael C.Huang, and Jose Renau, 15th  International Conference on Parallel Architectures and Compilation Techniques (<strong>PACT</strong>), September 2006.</description>
	
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        <pubDate>Fri, 01 Sep 2006 00:00:00 +0000</pubDate>
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	<title>New Paper: Printed Circuit Board Layout Time Estimation</title>
        
          <link>docs/wced06.pdf</link>
        
	<description>Cyrus  Bazeghi  and  Jose Renau,  7th  Workshop  on Complexity-Effective Design (<strong>WCED</strong>),  held in conjunction with ISCA-33, June 2006.</description>
	
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        <pubDate>Thu, 01 Jun 2006 00:00:00 +0000</pubDate>
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	<title>New Paper: SCOORE Santa Cruz Out-of-Order RISC Engine, FPGA Design Issues</title>
        
          <link>docs/warp06.pdf</link>
        
	<description>Francisco J.  Mesa-Martinez, Abhishek Sharma, Andrew W.  Hill, Carlos A.  Cabrera, Cyrus Bazeghi, Hari Kolakaleti, Joseph Nayfach, Keertika Singh, Kevin S. Halle, Matthew D. Fischler, Melisa Nuñez, Sangeetha Nair, Suraj Narender Kurapati, Wael Ali Ashmawi, and Jose Renau , Workshop on Architectural Research Prototyping (<strong>WARP</strong>), held inconjunction with ISCA-33, June 2006.</description>
	
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        <pubDate>Thu, 01 Jun 2006 00:00:00 +0000</pubDate>
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	<title>IES Berkeley/France Fund ($9K)</title>
	
	<description>This small grant is shared with <a href="http://www-rocq.inria.fr/~acohen/index.html.en">Albert Cohen</a> from INRIA. The objective is to establish a collaboration between the two centers.
	</description>
	
	
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        <pubDate>Mon, 01 May 2006 00:00:00 +0000</pubDate>
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	<title>New Paper: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses</title>
        
          <link>docs/cava_taco.pdf</link>
        
	<description>Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, ACM's Transactions on Architecture and Code Optimization (<strong>TACO</strong>), March 2006.</description>
	
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        <pubDate>Wed, 01 Mar 2006 00:00:00 +0000</pubDate>
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	<title>New Paper: POSH A TLS Compiler that Exploits Program Structure</title>
        
          <link>docs/ppopp06.pdf</link>
        
	<description>Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (<strong>PPoPP</strong>), March 2006.</description>
	
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        <pubDate>Wed, 01 Mar 2006 00:00:00 +0000</pubDate>
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	<title>Special Research Grant from UCSC ($12K)</title>
	
	<description>Small explorative grant to rent/purchase equipment to get preliminary results on thermal projects.
	</description>
	
	
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        <pubDate>Wed, 01 Feb 2006 00:00:00 +0000</pubDate>
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	<title>NASA/UARC "Checkpointed Fault Tolerant FPGA Systems" ($50K)</title>
	
	<description>Grant to support the development of the SCOORE project.
	</description>
	
	
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        <pubDate>Fri, 20 Jan 2006 00:00:00 +0000</pubDate>
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	<title>NSF CAREER ($400K)</title>
	
	<description>The goal of this CAREER is to understand, estimate, and reduce processor design complexity. To do so, the PI plans to develop uComplexity metrics to understand and estimate processor design complexity. The uComplexity metric consist of three main parts, namely a procedure to account for the contributions of the different components in the design, accurate statistical regression of experimental measures using a nonlinear mixed-effects model, and a productivity adjustment to account for the productivities of different teams. Once the metrics are developed, the we plan to develop new approaches to reduce processor design complexity.
	</description>
	
	
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        <pubDate>Fri, 20 Jan 2006 00:00:00 +0000</pubDate>
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	<title>New Paper: Energy-Efficient Thread-Level Speculation on a CMP</title>
        
          <link>docs/toppicks06.pdf</link>
        
	<description>Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas, IEEE Micro Special Issue <strong>Micro's Top Picks</strong> from Computer Architecture Conferences, January-February 2006.</description>
	
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        <pubDate>Sun, 01 Jan 2006 00:00:00 +0000</pubDate>
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	<title>New Paper: uComplexity Estimating Processor Design Effort</title>
        
          <link>docs/ucomplex.pdf</link>
        
	<description>Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau. 38th International Symposium on Microarchitecture (<strong>MICRO</strong>), November 2005.</description>
	
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        <pubDate>Tue, 01 Nov 2005 00:00:00 +0000</pubDate>
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	<title>Sun grid donation of 100K CPU hours</title>
	
	<description>Sun has donated 100K CPU on their <a href="http://www.sun.com/service/sungrid/index.jsp">sungrid</a> project. We are not going to have CPU constraints the next year.
	</description>
	
	
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        <pubDate>Sat, 01 Oct 2005 00:00:00 +0000</pubDate>
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	<title>Sun Niagara donation</title>
	
	<description>Sun donated a Niagara (T1) machine to our group. Thanks for the support.
	</description>
	
	
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        <pubDate>Sat, 01 Oct 2005 00:00:00 +0000</pubDate>
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	<title>New Paper: POSH A Profiler-Enhanced TLS Compiler that Leverages Program Structure</title>
        
          <link>docs/posh.pdf</link>
        
	<description>Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (<strong>P=AC2</strong>), September 2005.</description>
	
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        <pubDate>Thu, 01 Sep 2005 00:00:00 +0000</pubDate>
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	<title>New Paper: Thread-Level Speculation on a CMP Can Be Energy Efficient</title>
        
          <link>docs/ics05_power.pdf</link>
        
	<description>Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (<strong>ICS</strong>), June 2005.</description>
	
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        <pubDate>Wed, 01 Jun 2005 00:00:00 +0000</pubDate>
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	<title>New Paper: Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors Microarchitecture and Compilation</title>
        
          <link>docs/ics05_ooo.pdf</link>
        
	<description>Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (<strong>ICS</strong>), June 2005.</description>
	
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        <pubDate>Wed, 01 Jun 2005 00:00:00 +0000</pubDate>
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	<title>Altera Equipment Donation</title>
	
	<description>We have floating Quartus licenses.
	</description>
	
	
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        <pubDate>Fri, 01 Apr 2005 00:00:00 +0000</pubDate>
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	<title>New Paper: CAVA Hiding L2 Misses with Checkpoint-Assisted Value Prediction</title>
        
          <link>docs/cava04.pdf</link>
        
	<description>Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (<strong>TCCA</strong>), Dec 2004.</description>
	
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        <pubDate>Wed, 01 Dec 2004 00:00:00 +0000</pubDate>
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	<title>HPCS Complexity Management (Prime DoD/DARPA, Agency UIUC)</title>
	
	<description>Small grant to purchase some equipment.
	</description>
	
	
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        <pubDate>Fri, 01 Oct 2004 00:00:00 +0000</pubDate>
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	<title>UCSC Faculty Development award ($2K)</title>
	
	<description>First small grant for our group.
	</description>
	
	
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        <pubDate>Thu, 01 Jul 2004 00:00:00 +0000</pubDate>
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	<title>New Paper: Managing Multiple Low-Power Adaptation Techniques The Positional Approach</title>
        
          <link>docs/ieeecomputer03.pdf</link>
        
	<description>Michael Huang, Jose Renau and Josep Torrellas, Sidebar on Special Issue on Power-Aware Computing, (<strong>IEEE Computer</strong>), December 2003.</description>
	
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        <pubDate>Mon, 01 Sep 2003 00:00:00 +0000</pubDate>
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	<title>New Paper: Positional Adaptation of Processors Application to Energy Reduction</title>
        
          <link>docs/isca03.pdf</link>
        
	<description>Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (<strong>ISCA</strong>), June 2003.</description>
	
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        <pubDate>Sun, 01 Jun 2003 00:00:00 +0000</pubDate>
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	<title>New Paper: Programming a Parallel Intelligent Memory System</title>
        
          <link>docs/ppopp03.pdf</link>
        
	<description>Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (<strong>PPoPP</strong>), June 2003.</description>
	
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        <pubDate>Sun, 01 Jun 2003 00:00:00 +0000</pubDate>
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	<title>New Paper: Cherry Checkpointed Early Resource Recycling in Out-of-order Microprocessors</title>
        
          <link>docs/micro02.pdf</link>
        
	<description>Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (<strong>MICRO</strong>), November 2002.</description>
	
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        <pubDate>Fri, 01 Nov 2002 00:00:00 +0000</pubDate>
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	<title>New Paper: Energy-Efficient Hybrid Wakeup Logic</title>
        
          <link>docs/islped02.pdf</link>
        
	<description>Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (<strong>ISLPED</strong>), August 2002.</description>
	
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        <pubDate>Thu, 01 Aug 2002 00:00:00 +0000</pubDate>
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	<title>New Paper: A Framework for Dynamic Energy Efficiency and Temperature Management</title>
        
          <link>docs/jilpdeetm.pdf</link>
        
	<description>Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (<strong>JILP</strong>), 2002.</description>
	
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        <pubDate>Sat, 01 Jun 2002 00:00:00 +0000</pubDate>
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	<title>New Paper: Profiled-Based Energy Reduction for High-Performance Processors</title>
        
          <link>docs/fddo01.pdf</link>
        
	<description>Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001.</description>
	
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        <pubDate>Sat, 01 Dec 2001 00:00:00 +0000</pubDate>
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	<title>New Paper: Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips</title>
        
          <link>docs/verlag00.pdf</link>
        
	<description>Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol.  2107) by Springer-Verlag, 2001.</description>
	
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        <pubDate>Fri, 01 Jun 2001 00:00:00 +0000</pubDate>
      </item>
    
      
      
      
      <item>
	
	<title>New Paper: Cache Decomposition for Energy-Efficient Processors</title>
        
          <link>docs/islped01.pdf</link>
        
	<description>Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (<strong>ISLPED</strong>), August 2001.</description>
	
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        <pubDate>Wed, 01 Aug 2001 00:00:00 +0000</pubDate>
      </item>
    
      
      
      
      <item>
	
	<title>New Paper: A Framework for Dynamic Energy Efficiency and Temperature Management</title>
        
          <link>docs/micro33.pdf</link>
        
	<description>Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (<strong>MICRO</strong>), December 2000.</description>
	
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        <pubDate>Fri, 01 Dec 2000 00:00:00 +0000</pubDate>
      </item>
    
      
      
      
      <item>
	
	<title>New Paper: Memory Hierarchies in Intelligent Memories Energy/Performance Design</title>
        
          <link>docs/w00hier.pdf</link>
        
	<description>Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000.</description>
	
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        <pubDate>Thu, 01 Jun 2000 00:00:00 +0000</pubDate>
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